Vertical-cavity surface emitting lasers (VCSELs) emit light perpendicular to the surface of the wafer plane. The structure of VCSELs allows for manufacturing advantages over the structure of edge-emitting lasers, such as fabricating complete individual VCSELs simultaneously on a single semiconductor wafer. These manufacturing advantages lead to efficiency and cost savings during fabrication while permitting each laser to be individually testable in situ. VCSELs are also easily fabricated into two-dimensional (2D) arrays, wherein each laser is individually controllable.
Currently, VCSELs and VCSEL arrays are used primarily for lower-power applications, such as in short-reach datacom (850 and 980 nm), telecommunications (1300-1550 nm), optical mice, and spectroscopy. Applications such as optical pumping, industrial cutting, medical and defense applications require the use of high power lasers. High power lasers have been dominated by edge-emitting lasers that have a high percentage of their emitting area consumed by laser apertures (e.g., through the use of longer cavity lasers, broad area lasers arranged in parallel bars, serial laser bar stacking).
Thus, obtaining high power density from a VCSEL array requires a combination of characteristics from the array. These characteristics include highly efficient laser diode pixels, effective thermal managements and waste heat extraction, low resistance electrical current injection, and a high fill-factor of VCSEL pixels in the array.
Increasing the fill-factor of VCSEL pixels in an array cannot be effectively accomplished by making an extremely large aperture for each VCSEL of a 2D array (or, simply having a single VCSEL with an extremely large aperture consuming most of the area of a wafer). It is understood that, for thermal reasons, smaller pixels more easily dissipate heat than a larger aperture device; the hottest center part of the smaller aperture VCSEL is closer to the cooler edge of the laser than for a larger aperture VCSEL. For this reason, larger pixels suffer a decline in performance because the center part of their apertures operates hotter than those of smaller pixels. Lateral electrical series resistance accounts for the majority of the rest of the reduction in series resistance as aperture diameters increase. As a result, larger diameter devices with top ring metal contacts suffer non-uniform current injection due to lateral resistance and thus suffer a decline in performance.
Furthermore, solutions increasing the number of VCSELs in a 2D array while simultaneously making the apertures smaller are unsatisfactory, as VCSELs with apertures having a diameter smaller than 3 μm are less efficient due to optical scattering from the edge current confinement areas separating each VCSEL.
Prior art VCSEL packing layouts also restrict the fill-factor of wafers including 2D VCSEL arrays. Prior art packing layouts, as illustrated in FIG. 1, include hexagonal packing with circular-shaped VCSEL pillars 100, square packing circular pillars 110, and square packing with square-shaped VCSEL pillars 120.
Thus, if high efficiency is needed to achieve high power VCSEL arrays, a method of producing higher fill-factor VCSEL arrays using high efficiency individual devices is needed.
Descriptions of certain details and implementations follow, including a description of the figures, which may depict some or all of the embodiments described below, as well as discussing other potential embodiments or implementations of the inventive concepts presented herein. An overview of embodiments of the invention is provided below, followed by a more detailed description with reference to the drawings.